下一代架構(gòu)將現(xiàn)存H8和M16C芯片特性與其他新科技相結(jié)合，為16位和32位MCU提供一個功能強大的綜合解決方案 倫敦5月21日新聞――瑞薩科技公司今天宣布其正在開發(fā)一種新型CPU架構(gòu)，這種架構(gòu)將在密碼安全，數(shù)據(jù)處理性能（MIPS/MHz）和功率消耗方面較前幾代微控制器（MCUs）具有革命性的加強。瑞薩科技將基于新型架構(gòu)提供兩個CPU，指向開拓16位和32位MCU市場，同時保持與現(xiàn)存MCU兼容。該架構(gòu)將為兩種MCU提供升級，為瑞薩科技的MCU用戶提供一種功能強大而引人注目的系統(tǒng)方案。 瑞薩科技目前提供的M16C和H8S 16位CPU和R32C 及H8SX 32位CPU新型架構(gòu)將具有創(chuàng)新的進步。同時通過CPU指令組，外圍設(shè)備寄存器組以及開發(fā)工具與現(xiàn)存CPU兼容。他將M16C和R32C CPU的優(yōu)越代碼效率與H8S和H8SX CPU的高速數(shù)據(jù)處理相結(jié)合。此外，新型CPU架構(gòu)將進一步增強低功率消耗和低噪音的特性。擁有這些兼容性，瑞薩科技的目標(biāo)是在代碼效率，數(shù)據(jù)處理性能全球最佳性能（MIPS/MHz），功率消耗以及成本競爭力方面達到世界最佳水平。代碼效率尤為重要，因為它通過使用更少的閃存空間幫助減小系統(tǒng)程序尺寸，降低系統(tǒng)整體成本。 通過該架構(gòu)，瑞薩科技旨在將代碼尺寸減小30％，CPU的功率消耗減少50％。 “由于功能強大的產(chǎn)品研發(fā)，經(jīng)過現(xiàn)場驗正的生產(chǎn)能力和豐富的系統(tǒng)開發(fā)環(huán)境，瑞薩的多種MCU產(chǎn)品已經(jīng)多年在嵌入式市場取得成功，”瑞薩科技公司MCU業(yè)務(wù)部董事會主席兼總經(jīng)理Hideharu Takebe說，“瑞薩的MCU每年贏得超過10，000項設(shè)計，在消費品，汽車系統(tǒng)，工業(yè)產(chǎn)品，辦公設(shè)備以及通信產(chǎn)品應(yīng)用領(lǐng)域不斷獲得認(rèn)可。為了響應(yīng)對16位和32位MCU產(chǎn)品不斷增長的需求，下一步我們將為16位和32位MCU市場開發(fā)下一代簡單架構(gòu)CPU。宣布這個消息后，我們目前的和未來的客戶可以相信瑞薩科技不僅致力于支持我們現(xiàn)存的MCU家族產(chǎn)品，也提供可靠的升級，瑞薩建立在其全球領(lǐng)先地位的基礎(chǔ)至上，將繼續(xù)引領(lǐng)MCU市場。 在瑞薩科技公司慶祝其成立四周年之際也正在進行下一代16位和32位CISC＊³ CPU的開發(fā)。公司計劃投入相當(dāng)?shù)馁Y源到此項工程，預(yù)計新一代CPU將進一步擴展瑞薩科技的業(yè)務(wù)。 新型CPU開發(fā) 結(jié)合新型架構(gòu)CPU的設(shè)備將涵蓋16位和32位CISC性能，使用簡單，并將縮短系統(tǒng)制造開發(fā)時間。此外，通過保持與現(xiàn)存產(chǎn)品的兼容性，新型CPU將使得目前的和將來的客戶保持其工程投資。 瑞薩標(biāo)準(zhǔn)的開發(fā)環(huán)境，高性能的嵌入式工作站還將為其新型CPU和現(xiàn)存的MCU提供全面支持。這將簡化移動現(xiàn)存產(chǎn)品中的軟件資源到基于新型CPU的MCU，并將加速新軟件的開發(fā)和調(diào)試。為了確保客戶能得到多種開發(fā)工具的選擇，瑞薩將根據(jù)其聯(lián)盟合作計劃繼續(xù)與第三方公司合作，通過網(wǎng)絡(luò)積極共享新型架構(gòu)的信息。公司將繼續(xù)開發(fā)新產(chǎn)品，運用目前的MCU產(chǎn)品為客戶提供支持。2008年早期將推出新型CPU的規(guī)格，預(yù)計第二季度將推出配置新型CPU的設(shè)備：基于瑞薩的90nm閃存處理器的, CY2009。汽車應(yīng)用設(shè)備預(yù)計將在非機動車應(yīng)用設(shè)備推出后推出，推出時間由市場需求決定。 original text： [COLOR=#708090]Renesas Technology to develop new CPU architecture for microcontrollers The next-generation architecture will combine the features of the existing H8 and M16C cores along with other new technologies, delivering a powerful, comprehensive solution for 16- and 32-bit MCUs. LONDON, UK – 21st May 2007 — Renesas Technology Corp. today announced that it is in the process of developing a new CPU architecture that will provide revolutionary enhancements over previous generation microcontrollers （MCUs） in code-efficiency＊¹, processing performance （MIPS/MHz）, and power consumption. Based on the new architecture, Renesas will offer two CPUs to address 16- and 32-bit markets, while maintaining compatibility with Renesas‘ existing MCUs. The architecture will provide upgrade paths for both markets, delivering a powerful and compelling system solution for Renesas‘ MCU customers. The new architecture will have innovative advances over the M16C and H8S 16-bit CPUs and R32C and H8SX 32-bit CPUs that Renesas Technology currently offers, while offering compatibility with the existing families in terms of CPU instruction sets, peripheral register sets and development tools. It will combine the excellent code efficiency of the M16C and R32C CPUs with the high-speed data processing of the H8S and H8SX CPUs. Moreover, the new CPU architecture will further extend the low power consumption and low noise characteristics of both family lines. With these capabilities, Renesas aims to achieve the world‘s best overall performance considering code efficiency, processing performance （MIPS/MHz）, power consumption and cost competitiveness. Code efficiency is especially important since it helps to minimize system program size and reduce overall system cost by allowing the use of less flash memory. By employing this new architecture, Renesas aims to reduce code size by 30% and CPU power dissipation by 50%. “Renesas‘ broad MCU product offerings have been successful in the embedded market for many years, backed by powerful product development, field-proven manufacturing capabilities and a rich system-development environment,” said Hideharu Takebe, board director and general manager, MCU business group, Renesas Technology Corp. “Renesas‘ MCUs have won over 10,000 designs annually, gaining accelerated acceptance in applications such as consumer products, automotive systems, industrial products, office equipment, and communication products. As a next step, we are developing next-generation CPUs for 16- and 32-bit markets under a single architecture, in response to the growing demand for both 16- and 32-bit MCU products. With this announcement, our present and future customers can be assured that Renesas is committed not only to supporting our existing MCU product families, but also to providing a solid upgrade path. Renesas continues to lead the MCU market by building on its global leadership. （No. 1 share＊² worldwide）” The project to develop the next-generation 16- and 32-bit CISC＊³ CPUs is underway as Renesas celebrates the fourth anniversary of its establishment. The company plans to dedicate substantial resources to the project, and the new CPUs are expected to further expand Renesas‘ MCU business. New CPU Development Devices incorporating CPUs based on the new architecture will scale from 16-bit to 32-bit CISC performance. They will be very easy to use and will shorten development times for system manufacturers. Moreover, by maintaining compatibility with existing products, the new CPUs will allow existing and future customers to preserve their engineering investments. Renesas‘ standard development environment, the High-performance Embedded Workshop, will also provide total support for the new CPUs as well as its existing MCUs. This will simplify the migration of software resources from the existing products to MCUs based on the new CPUs, and accelerate the development and debugging of new software. To ensure that customers will have access to a wide selection of development tools, Renesas will continue to work with third-party companies and actively share information concerning the new architecture via the Web under Renesas‘ Alliance Partner Program. The company will continue to develop new products and provide support for customers using currently available MCU products. The specifications of the new CPUs will be released in early 2008 and the first devices with the new CPUs are expected to become available during Q2, CY2009 based on Renesas‘ 90nm flash MCU process. Devices for automotive applications are expected to be introduced after those for non-automotive applications, with the schedule determined by market requirements.[/COLOR]